Systems Observatory
Three constellations, linked lessons and independent example runs. PCIe is a branching tree, the IOMMU is stacked translation layers, and power is a cycle of states. Pick a way through: the numbered stars form a route, with each border introducing a new system idea. Choose another route, or press the chosen one again to list all three; without JavaScript all three lists remain available. Or follow one card through all three in a combined lab. New to confidential computing? Start with The Vault.
Start here
These linked lessons use independent examples to introduce PCIe, DMA, translation, faults and power.
- PCIe · Reading lspci Learn what the fields show in this example.
- PCIe · Before DMA: PCIe setup See when a device may write at all.
- PCIe to IOMMU: requester identity tells the IOMMU which device made a request.
- IOMMU · Start: 16 bytes Follow this lesson's example write toward memory.
- IOMMU · IOMMU foundations Learn how translation tables are structured.
- IOMMU · Faults & recovery Explore fault causes and recovery in this example.
- IOMMU to Power: the final lesson introduces CPU, device and link idle before wake.
- Power · Power states, idle & wake First distinguish CPU, device and link idle; then follow wake.
Run the whole journey in one lab: one NIC, three stops →
Explore the details
For practitioners: go straight to the fields, formats and corner cases.
- PCIe · PASID, ATS & SR-IOV PASID, ATS, PRI and SR-IOV, as lspci prints them.
- PCIe · Switch: bridges & AtomicOps What every port on the path must support.
- PCIe to IOMMU: PASID and ATS add request context that can help distinguish clients.
- IOMMU · Request identity Request identity: 112 test recipes.
- IOMMU · IOTLB & cache state The IOTLB, and what an invalidation must cover.
- IOMMU · AMD reference The selected table and log entry formats, bit by bit.
- Power adds a separate view of idle and wake: a sleeping PCIe link can save watts but delay a request.
- Power · PCIe link power ASPM and link states.
Investigate a failure
How I validate: separate what was intended, what was observed and what proves it.
- PCIe · Before DMA: PCIe setup The write never happened. Was BusMaster off, or was it blocked?
- PCIe to IOMMU: once a request is sent, the IOMMU's evidence takes over.
- IOMMU · IOMMU foundations Allowed control, denied probe, recovery control.
- IOMMU · IOTLB & cache state It passed, on the wrong page. Where did the bytes go?
- IOMMU · Faults & recovery A fault record is not a recovery.
- Power adds a separate example of wake state: resume is another chance to lose state.
- Power · Device sleep and wake Did the device come back as it was?
Now try one: the test passed, so find out why →