A network card (NIC) writes 16 bytes to an address it was given. The
IOMMU, the device's MMU, translates that address into a system
physical address (SPA) in RAM and checks the permission. Take the
five-minute story below, or go straight to the full trace.
Spec rule: the IOMMU translates a device address using the Device Table Entry and page tables, and a missing or forbidden page stops the request (AMD IOMMU spec 48882 rev 3.11, chapter 2).
Platform assumption: whether hardware caches an absent entry, and how a driver recovers, vary by platform and driver.
Teaching model: one fixture with a 16-byte write, deterministic caching and a made-up NIC; the Arm SMMUv3 backend is a separate teaching model.
THE FIVE-MINUTE STORY · PREDICT, THEN RUN
Who decides where a card may write?
Network cardwrites 16 bytes to device address 0x800ABC
→
IOMMUlooks up the address and checks the operation
Model: this site's smaller AMD-style teaching model, running in JavaScript in your browser. It is not dmakit; the dmakit code lab is the library. Real hardware and other vendors' IOMMUs are reference-only here.
How does a device address reach memory?
Repair the path. Prove the transfer.
Three observations in the live fixture. No timer, no score penalty. The suggested next action is outlined.
To observe · Missing page blocks the request
To observe · Repair alone still leaves stale state
To observe · Synchronize, retry, verify 16 bytes
Back to the story · This model deliberately retains the absent entry. Hardware need not cache an absent mapping. Background gravity is decorative and does not represent address translation.
What kind of claim is this?
Raw JSON of this eventEvents inspected so far in this run
Which part answers your question?
Select a node to distinguish configuration, payload and software
actions.