PCIe / PREREQUISITE LAB

Can this device issue the request yet?

Enable bus mastering, prepare the software mapping, and check the DMA address range. Change one condition and inspect what prevents the request.

Watch one DMA write travel from the card to a cell of DRAM → (animated showcase)

What claims does this page make? 2 points

Spec rule: bus mastering is bit 2 of the PCI Command register, and a posted write gets no reply while a read gets Completions (PCI specifications, members only, so not checked here).
Teaching model: the mapping flag, the DMA mask and the rejection of a zero-length transfer are this page's own simplified policy, not PCIe configuration registers or packet rules.

Check the setup

Model result

Scope of this model

This card checks whether a DMA descriptor is ready. It does not execute an IOMMU translation, send a packet, or transfer bytes. Software setup, hardware traffic and observed completion are separate.

Start with a prepared write. Then disable bus mastering: the descriptor is blocked before any modelled IOMMU request.

A zero-length descriptor is rejected by this fixture’s software policy; this is not a universal rule for PCIe packets. No raw TLP encoding is fabricated.

A write is posted: the device gets no reply. A read is non-posted: the data comes back in one or more Completion packets (TLPs, PCIe's transaction-layer packets).

Evidence	What it establishes
PCIe Completion traffic	Response to a non-posted request; not a posted-write acknowledgement.
NIC work completion	Device-specific work status, distinct from a TLP.
IOMMU invalidation completion	The specified synchronization condition, not payload completion.
Interrupt acknowledgement	Notification handling, not mapping repair.

A software descriptor may generate multiple requests. The Translation lab chooses 256-byte requests and 4 KiB boundaries. Optional PASID/ATS require their own capability controls. Translation success alone does not establish CPU cache visibility, ordering or ownership.

The requirement

Within this simplified policy, a transfer needs bus mastering enabled, an available mapping, a nonzero length, and a complete range within the device’s DMA address mask.

The model

The Command register’s bus-master bit is represented in a synthetic device structure. The mapping flag and DMA mask are separate software state; they are not invented PCIe configuration registers. Enabling bus mastering alone does not prepare a DMA buffer or establish its mapping.

What the tests check

Reject a transfer when bus mastering is disabled.
Enable the bit and verify that a missing mapping still blocks the transfer.
Accept a valid range and the final single byte allowed by the mask.
Reject a boundary-crossing range, a zero-length request, and a revoked mapping.

Try a change

Change the device’s mask to 0xffffULL, then change the valid test address to 0x10000. Observe the range check reject a transfer that the previous mask permitted. The “last address” check fails too; its expectation assumes the 32-bit mask. Keep the expected result explicit when adapting a test.

C++ experiment

Default: C++23 · choose GCC or Clang below

Edit the source, then run the tests. Compilation provided by Compiler Explorer. Clicking Run sends the code to that external service. Use only public, non-confidential code.

Editable source

// Independent synthetic policy model. No PCI configuration or DMA access occurs.
#include <cstdint>
#include <iostream>
#include <string_view>

constexpr std::uint16_t bus_master = 1u << 2; // PCI Command register bit.

struct Device {
    std::uint16_t command = 0;
    bool mapping_ready = false; // Abstract mapping and lifetime precondition.
    std::uint64_t dma_mask = 0xffffffffULL;
};

// Validates this model's policy, not all conditions required by real hardware.
std::string_view validate(const Device& d, std::uint64_t address, std::uint64_t size)
{
    if (!(d.command & bus_master)) {
        return "bus mastering disabled";
    }
    if (!d.mapping_ready) {
        return "mapping unavailable";
    }
    if (!size) {
        return "empty transfer";
    }
    // Subtraction avoids overflow in address + size - 1.
    if (address > d.dma_mask || size - 1 > d.dma_mask - address) {
        return "DMA range exceeds mask";
    }
    return "ready in model";
}

int main()
{
    Device d;
    int failures = 0;
    auto check = [&](std::string_view got, std::string_view expected, const char* name) {
        bool ok = got == expected;
        std::cout << (ok ? "PASS " : "FAIL ") << name << " : " << got << '\n';
        failures += !ok;
    };
    check(validate(d, 0x1000, 4096), "bus mastering disabled", "initial state");
    d.command |= bus_master; // Synthetic read-modify-write; preserves other bits.
    check(validate(d, 0x1000, 4096), "mapping unavailable", "enable alone is insufficient");
    d.mapping_ready = true;
    check(validate(d, 0x1000, 4096), "ready in model", "valid range");
    check(validate(d, 0xffffffff, 1), "ready in model", "last address");
    check(validate(d, 0xffffffff, 2), "DMA range exceeds mask", "crossing mask boundary");
    check(validate(d, 0, 0), "empty transfer", "zero length");
    check(validate(d, ~0ULL, 2), "DMA range exceeds mask", "overflowing range");
    d.mapping_ready = false;
    check(validate(d, 0x1000, 4096), "mapping unavailable", "mapping revoked");
    return failures ? 1 : 0;
}

Download .cpp

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Compiler & test output

Run the example to see actual output here.

If the external service is unavailable, copy the source and open Compiler Explorer, or compile locally with g++ -std=c++23 example.cpp -o example and run ./example.

What this does not establish

No configuration space is accessed and no DMA is performed. The example does not model descriptor rings, BAR setup, requester identity, actual IOMMU permissions, ordering, cache coherency, device-specific registers, or transfer completion. It checks a narrow policy, not PCIe compliance or production readiness.

Public references

Personal educational material; not an employer publication or endorsement.

This is where the PCIe guide ends: the device may now send its request. The IOMMU guide picks it up at the IOMMU.

Explore PCIe request splitting and negative tests →