From raw bits to a checked path.

1 / Read the sixteen bytes

All ten AMD command headers and fourteen event families, including enhanced invalid-device and PPR response variants. Bytes are shown in memory order, least significant byte first. This inspector does not submit commands to hardware.

Reserved-bit rejection, unsupported capability, ignored field and software protocol restriction are different diagnoses. A decoded event is evidence, not a command to repair or retry the request. Use the semantic command and halt/restart lab.

Publish → fetch → complete

Queues the raw command edited above into the existing serial buffer model. The decoded range and identifiers remain visible; effects use one selected synthetic cache scope. This does not claim range-expansion, physical completion stores or a real PCIe fabric.

Publication, local invalidation, remote acknowledgment and completion are separate observations. This fixture withholds the acknowledgment indefinitely: the wait stays pending and page reuse stays unsafe. It does not model the configured InvTimeOut recovery path (IOTLB_INV_TIMEOUT); the virtual-IOMMU chapter models that one. A finished command never counts as a verified endpoint invalidation. Completion wait supplies no missing invalidation; its f bit controls subsequent command launch. Use the Faults & recovery chapter for halt/disable/repair/restart. RESET_VMMIO marks the guest context for reconfiguration.

PASID capability versus missing context

2 / Walk an independent Arm path

Stall mode represents an on-chip client. PCIe streams must use Terminate; PRI is a separate endpoint request/response protocol. This profile assumes event recording is enabled.

Linear StreamID selection, one CD per configured stream, non-secure 48-bit addresses and 4 KiB granule. Stage-1 pages and stage-2 blocks retain offsets. STE/CD words and 32-byte EVTQ records are semantic here; advanced memory attributes, HTTU and security extensions remain reference-only.

3 / Registers and dual logs

Choose an operation.

Program the queue, respect its owner

Focused register programming with legal geometry. AMD pointers are byte offsets; Arm pointers combine entry index and wrap. Unsafe software writes are rejected by this teaching guard without fabricating an architectural event.

Arm CR0 writes and CR0ACK observations are separate. Direct enable/disable buttons perform both steps. GERRORN must match GERROR; repairing the offending command remains a separate action in the Arm execution lab. AMD HEAD/TAIL are RW registers with state-dependent ownership, not universally RO. This panel has no real memory backing; record contents and overflow recovery live in the adjacent queue labs.

4 / An interrupt is a different request

Vector 81 → destination 2 is the default basic remap.

Editing fields prepares an entry; publish it to change backing memory, then deliver to inspect caching. For x2APIC, destination bits 23:0 occupy IRTE bits 31:8 and destination bits 31:24 occupy bits 127:120. GAEn is required even with GuestMode=0. Guest IsRun, destination, GALogIntr, GAPPIDis and GATag are not cached. The vector and backing-page root require invalidation.

Try RemapEn=0, index 8, an unaligned guest root, or disabled x2APIC prerequisites. In guest mode a pending virtual IRR bit survives GA-log overflow and draining. Three GA records is a teaching capacity. Reset recovers this fixture’s overflow; the Command & event buffers chapter shows the full halt/restart sequence. GAPPIDis is reserved in this selected profile. APIC bus delivery, EOI, GAPPI and SNP AVIC are reference-only. Arm GIC/ITS interrupt translation is separate from SMMUv3.

5 / Did this traffic cross your protection unit?

Every path uses the same intended deny policy. The selected routing assumptions determine whether that policy is reached. Peer routing, requester aliases and ACS depend on the platform (see IOMMU groups & ACS); they are not universal bypass claims.

6 / From driver mapping to hardware DMA

Drivers use the DMA API; the hardware does not call Linux functions. CPU/device cache ownership is distinct from IOMMU translation invalidation. The layer boundaries are illustrated by Lenovo LP1467; exact kernel helper names and call chains vary by release.

Coverage you can inspect

Scope labels distinguish a packed codec, executable semantic state, reference-only features and hardware evidence. A current specification baseline does not imply every optional capability exists.

H.a §2.10 permits constrained adoption of next-version features. This selector shows when features were introduced, not a substitute for reading implemented IDR capabilities.

H.a §§4.1.3/4.1.5 permit unspecified command RES0 fields to be ignored or detected. The RES0 selector represents that implementation policy; unknown opcodes remain illegal. Scenario JSON accepts expected or allowed_outcomes, with outcome_sources documenting the relevant clauses.

Inspect an Arm event record

Exact 32-byte layouts for ten H.a event types, using a non-secure base-feature profile. Unknown values and unsupported advanced fields remain visible. RnW=1 means read; this is different from AMD RW=1 meaning write.

Implementation coverage

Download machine-readable coverage and source registry. Executable codec means packed bytes can be encoded/decoded; semantic means a bounded teaching state machine.

References and limits

• AMD 48882-PUB rev 3.11, April 2026: §§2.2.5, 2.4–2.7 and Chapter 3. Publisher PDF.
• Arm IHI 0070 H.a, 6 March 2026: §§2.2–2.10, 3.5, 3.13, Chapters 4–7. Arm documentation.
• Lenovo LP1467 (2021); Linux DMA mapping guide; Linux IOMMUFD.

No real MMIO, device DMA, memory poison, firmware security flow or CPU memory-barrier timing is exercised. The C++ download remains the existing AMD DMA model; these new JavaScript scenarios are not claimed as C++ features.