{
  "release": "r13",
  "sources": [
    {
      "id": "amd",
      "title": "AMD I/O Virtualization Technology (IOMMU) Specification",
      "document": "48882-PUB",
      "revision": "3.11",
      "date": "April 2026",
      "provenance": "Publisher PDF",
      "url": "https://docs.amd.com/api/khub/documents/2oKZlc87KNCKiT3B~xJjHg/content",
      "reviewed": "2026-09-27"
    },
    {
      "id": "arm",
      "title": "Arm System Memory Management Unit Architecture Specification",
      "document": "IHI 0070",
      "revision": "H.a",
      "date": "6 March 2026",
      "provenance": "Publisher page for H.a",
      "url": "https://developer.arm.com/documentation/ihi0070/ha",
      "reviewed": "2026-09-27"
    },
    {
      "id": "linux",
      "title": "Linux AMD IOMMU implementation",
      "revision": "80a4e3ad8daba66915a9bdf0fcae5831cc8dbd5f",
      "date": "2026-09-27",
      "url": "https://github.com/torvalds/linux/blob/80a4e3ad8daba66915a9bdf0fcae5831cc8dbd5f/drivers/iommu/amd/iommu.c",
      "upstream": "https://github.com/torvalds/linux/blob/master/drivers/iommu/amd/iommu.c",
      "scope": "Selected command construction and field constants; not a hardware oracle",
      "reviewed": "2026-09-27"
    },
    {
      "id": "lenovo",
      "title": "An Introduction to IOMMU Infrastructure in the Linux Kernel",
      "document": "LP1467",
      "revision": "2021 paper",
      "url": "https://lenovopress.lenovo.com/lp1467.pdf",
      "scope": "Historical Linux layering; helpers vary by kernel release. Context only: the Passthrough chapter checks its claims against the AMD specification and Linux v6.18, and corrects this paper's reading of iommu=pt",
      "reviewed": "2026-09-27"
    },
    {
      "id": "intel-vtd",
      "title": "Intel Virtualization Technology for Directed I/O",
      "document": "D51397-017",
      "revision": "5.0",
      "date": "August 2024",
      "url": "https://cdrdv2-public.intel.com/831418/vt-directed-io-spec.pdf",
      "scope": "Pinned comparison of first-stage roots and maintenance, and the glossary's concept names; no Intel executable backend; not claimed latest",
      "reviewed": "2026-09-27"
    },
    {
      "id": "intel-cpu",
      "title": "Intel SDM Volume 3A",
      "document": "253668-060US",
      "revision": "September 2016",
      "url": "https://www.intel.sg/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf",
      "scope": "Older pinned four-level CR3/PCID baseline only; excludes modern optional CPU features",
      "reviewed": "2026-09-27"
    }
  ],
  "coverage": [
    {
      "feature": "Linux DMA/SWIOTLB with emulated AMD Event log",
      "status": "SEMANTIC",
      "source": "Pinned Linux DMA-IOMMU/SWIOTLB source; AMD 48882 3.11 Event profile",
      "module": "linux-dma-model.mjs",
      "testFile": "tests/iommu-dma.test.mjs",
      "testId": "R13 Linux hybrid",
      "scope": "Independent browser model; not a running Linux kernel; SWIOTLB alone has no IOMMU protection; reduced allocator/Event ring; no PRI/GA invented"
    },
    {
      "feature": "Shared CPU CR3 / AMD guest table memory",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §§2.2.1,2.2.6.3,2.2.7.3,2.4.3–2.4.4; CPU CR3 profile",
      "module": "shared-tables-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "R13 shared roots",
      "scope": "Five bounded experiments; Intel/Arm comparisons reference-only; 4-level/4 KiB; independent CPU/IOMMU/ATC; no host-cache or wire-level protocol model"
    },
    {
      "feature": "Cache experiment: CACHE-DMA-01",
      "status": "SEMANTIC",
      "source": "AMD §2.4.3",
      "module": "cache-story-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "CACHE-DMA-01",
      "scope": "Deterministic retained-entry schedule; no real DMA, CPU delivery or cache timing"
    },
    {
      "feature": "Cache experiment: CACHE-DMA-02",
      "status": "SEMANTIC",
      "source": "AMD §2.2.7.3; NpCache p.206",
      "module": "cache-story-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "CACHE-DMA-02",
      "scope": "Deterministic retained-entry schedule; no real DMA, CPU delivery or cache timing"
    },
    {
      "feature": "Cache experiment: CACHE-IRQ-01",
      "status": "SEMANTIC",
      "source": "AMD Control[59] p.217; §2.4.5",
      "module": "cache-story-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "CACHE-IRQ-01",
      "scope": "Deterministic retained-entry schedule; no real DMA, CPU delivery or cache timing"
    },
    {
      "feature": "Cache experiment: CACHE-IRQ-02",
      "status": "SEMANTIC",
      "source": "AMD §§2.2.5.2,2.3.2",
      "module": "cache-story-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "CACHE-IRQ-02",
      "scope": "Deterministic retained-entry schedule; no real DMA, CPU delivery or cache timing"
    },
    {
      "feature": "Cache experiment: CACHE-ATS-01",
      "status": "SEMANTIC",
      "source": "AMD §§2.4.3–2.4.4,2.4.11",
      "module": "cache-story-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "CACHE-ATS-01",
      "scope": "Deterministic retained-entry schedule; no real DMA, CPU delivery or cache timing"
    },
    {
      "feature": "Cache experiment: CROSS-IRQ-01",
      "status": "SEMANTIC",
      "source": "AMD §§2.2.5,2.4.5",
      "module": "cache-story-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "CROSS-IRQ-01",
      "scope": "Deterministic retained-entry schedule; no real DMA, CPU delivery or cache timing"
    },
    {
      "feature": "Cache experiment: CACHE-GA-01",
      "status": "SEMANTIC",
      "source": "AMD §§2.2.5.2,2.7",
      "module": "cache-story-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "CACHE-GA-01",
      "scope": "Deterministic retained-entry schedule; no real DMA, CPU delivery or cache timing"
    },
    {
      "feature": "Cache experiment: COHERENCY-01",
      "status": "SEMANTIC",
      "source": "Linux DMA API: streaming ownership / coherent ordering",
      "module": "cache-story-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "COHERENCY-01",
      "scope": "Deterministic retained-entry schedule; no real DMA, CPU delivery or cache timing"
    },
    {
      "feature": "Cache experiment: ARM-CACHE-01",
      "status": "SEMANTIC",
      "source": "Arm H.a §§3.21,4.3–4.5,4.7.3",
      "module": "cache-story-model.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "ARM-CACHE-01",
      "scope": "One CMDQ; no GIC/ITS or all optional SMMUv3 features"
    },
    {
      "feature": "Warm-cache mutation and shared NIC memory",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §§2.4.2–2.4.5,2.4.11",
      "module": "cache-experiments.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "R12 warm cache mutation",
      "scope": "Successful entries retained deterministically; separate completed scopes; two requesters share RAM with distinct permissions; no ATC, eviction or concurrent ordering model"
    },
    {
      "feature": "DMA lesson: first-request",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §2.2.3, §2.3",
      "module": "../dma-lessons.mjs",
      "testFile": "tests/iommu-dma.test.mjs",
      "testId": "DMA-FIRST-BYTES",
      "scope": "Fixture host-16; requirements STORY-04, STORY-06, STORY-09, STORY-12; evaluated scope direction, destination, byte-count, payload-bytes, protected-memory; not architecture conformance"
    },
    {
      "feature": "DMA lesson: permission",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 Table 44, §2.2.3",
      "module": "../dma-lessons.mjs",
      "testFile": "tests/iommu-dma.test.mjs",
      "testId": "DMA-PERMISSION",
      "scope": "Fixture host-iw; requirements STORY-04, STORY-06, STORY-09, STORY-12; evaluated scope direction, destination, byte-count, payload-bytes, protected-memory; not architecture conformance"
    },
    {
      "feature": "DMA lesson: boundary",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 Table 44, §2.5.3",
      "module": "../dma-lessons.mjs",
      "testFile": "tests/iommu-dma.test.mjs",
      "testId": "DMA-PARTIAL-FAULT",
      "scope": "Fixture host-boundary; requirements STORY-04, STORY-06, STORY-09, STORY-12; evaluated scope direction, destination, byte-count, payload-bytes, protected-memory; not architecture conformance"
    },
    {
      "feature": "DMA lesson: record",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §2.5, §2.5.3",
      "module": "../dma-lessons.mjs",
      "testFile": "tests/iommu-dma.test.mjs",
      "testId": "DMA-RECORD-RETIRE",
      "scope": "Fixture host-pr-record; requirements STORY-04, STORY-06, STORY-09, STORY-12; evaluated scope byte-count-only; not architecture conformance"
    },
    {
      "feature": "DMA lesson: recovery",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §2.4.3, §2.4.11",
      "module": "../dma-lessons.mjs",
      "testFile": "tests/iommu-dma.test.mjs",
      "testId": "DMA-RECOVERY",
      "scope": "Fixture host-pr-recovery; requirements STORY-04, STORY-06, STORY-09, STORY-12; evaluated scope byte-count-only; not architecture conformance"
    },
    {
      "feature": "Live buffer fault playground",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §§2.4–2.7 / Arm H.a §§3.5,3.12–3.13",
      "module": "fault-playground.mjs",
      "testFile": "tests/iommu-cache-labs.test.mjs",
      "testId": "R12 command diagnostics",
      "scope": "Composes existing AMD/Arm models; reduced queues and selected recovery paths; no raw wire capture; its tests cover the AMD command and DMA diagnostics only"
    },
    {
      "feature": "Guest APIC backing and GA evidence",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §§2.2.5.2,2.7",
      "module": "architecture/amd/irte.mjs",
      "testFile": "tests/iommu-amd.test.mjs",
      "testId": "R12 Guest APIC literal",
      "scope": "4 KiB backing with virtual IRR only; exact GA record codec; no CPU arbitration, ISR or EOI"
    },
    {
      "feature": "DMA identity evidence classifier",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 Table 7, Tables 44/50/51; §2.2.9",
      "module": "request-evidence.mjs",
      "testFile": "tests/iommu-requests.test.mjs",
      "testId": "PASID enablement is not wire evidence",
      "scope": "Declared V=1/TV=1 profile; separates observed prefix, effective PASID and workload mismatch; no bus capture or payload execution"
    },
    {
      "feature": "PCIe request geometry",
      "status": "EXECUTABLE",
      "source": "AMD PG054 Error Detection; Intel 710 Series datasheet 4.1",
      "module": "pcie-requests.mjs",
      "testFile": "tests/iommu-requests.test.mjs",
      "testId": "PCIe literal boundary",
      "scope": "Contiguous Memory Read/Write only; 4K split, DW byte enables and MPS/MRRS; not a raw TLP codec or conformance suite"
    },
    {
      "feature": "Cross-architecture negative-test recipes",
      "status": "REFERENCE",
      "source": "AMD 3.11 / Arm H.a / public PCIe guidance",
      "module": "edge-cases.mjs",
      "testFile": "tests/iommu-registry.test.mjs",
      "testId": "Every test recipe",
      "scope": "112 sourced recipes; counts are not executed requirements; existing AMD catalogue reused"
    },
    {
      "feature": "AMD command/event codecs",
      "status": "EXECUTABLE",
      "source": "AMD 48882 3.11 §§2.4–2.5",
      "module": "architecture/amd/records.mjs",
      "testFile": "tests/iommu-amd.test.mjs",
      "testId": "all ten AMD command headers",
      "scope": "Ten command headers, fourteen event families; selected conditional variants"
    },
    {
      "feature": "AMD command execution",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §2.4.11",
      "module": "architecture/amd/command-session.mjs",
      "testFile": "tests/iommu-amd.test.mjs",
      "testId": "r9 raw command lifecycle",
      "scope": "One serial selected scope; range fields decoded but not expanded"
    },
    {
      "feature": "AMD DMA",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §§2.2–2.3",
      "module": "../iommu-dma.mjs",
      "testFile": "tests/iommu-dma.test.mjs",
      "testId": "r9 DMA",
      "scope": "1–65536-byte descriptor; repeating pattern 1–32 bytes; PML4/48-bit guest"
    },
    {
      "feature": "AMD IRTE / x2APIC",
      "status": "EXECUTABLE",
      "source": "AMD 48882 3.11 §§2.2.5.1–3",
      "module": "architecture/amd/irte.mjs",
      "testFile": "tests/iommu-amd.test.mjs",
      "testId": "r9 IRTE literal vectors",
      "scope": "32/128-bit packed codecs; cached/live-field and GA effects semantic"
    },
    {
      "feature": "AMD PASmax distinction",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §2.2.7.8, Table44",
      "module": "architecture/amd/pasid.mjs",
      "testFile": "tests/iommu-amd.test.mjs",
      "testId": "r9 PASmax",
      "scope": "Independent expert assessment; basic DMA model retains existing GLX guard"
    },
    {
      "feature": "AMD Event/PPR autoswap",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 §§2.5–2.6",
      "module": "architecture/amd/dual-log.mjs",
      "testFile": "tests/iommu-amd.test.mjs",
      "testId": "dual event and PPR banks",
      "scope": "One engine/two banks; reduced teaching capacity"
    },
    {
      "feature": "Register ownership",
      "status": "SEMANTIC",
      "source": "AMD 48882 3.11 Ch3 / Arm H.a §§3.5,6.3",
      "module": "architecture/shared/queue-registers.mjs",
      "testFile": "tests/iommu-amd.test.mjs",
      "testId": "r9 AMD raw queue registers",
      "scope": "Focused register geometry/ownership, CR0ACK and GERROR; no real MMIO"
    },
    {
      "feature": "Arm translation / stall / PRI",
      "status": "SEMANTIC",
      "source": "Arm IHI 0070 H.a §§3.3–3.13,4,7",
      "module": "architecture/arm/model.mjs",
      "testFile": "tests/iommu-arm.test.mjs",
      "testId": "Arm stalls retain events",
      "scope": "Non-secure OAS48, 4K granule, one CD per stream; semantic STE/CD"
    },
    {
      "feature": "Arm event codecs",
      "status": "EXECUTABLE",
      "source": "Arm IHI 0070 H.a §7.3",
      "module": "architecture/arm/events.mjs",
      "testFile": "tests/iommu-arm.test.mjs",
      "testId": "r9 ten Arm event IDs",
      "scope": "Ten exact 32-byte base-feature layouts; advanced flags unsupported"
    },
    {
      "feature": "Arm STE/CD/L1 descriptor codec",
      "status": "EXECUTABLE",
      "source": "Arm IHI 0070 H.a §§5.2,5.4 / Linux v6.18 arm-smmu-v3.h",
      "module": "architecture/arm/records.mjs",
      "testFile": "tests/iommu-arm.test.mjs",
      "testId": "STE, CD and descriptor fields sit where Linux v6.18 puts them",
      "scope": "Fields Linux defines only; the Arm SMMUv3 page lists the rest"
    },
    {
      "feature": "Arm command opcodes and layouts",
      "status": "EXECUTABLE",
      "source": "Arm IHI 0070 H.a Ch. 4 / Linux v6.18 CMDQ_OP_* (four opcodes from QEMU v10.1.0)",
      "module": "architecture/arm/spec.mjs",
      "testFile": "tests/iommu-arm.test.mjs",
      "testId": "commands carry their Linux (or QEMU) opcodes",
      "scope": "Opcodes and 16-byte layouts of 23 commands; not a full command decoder"
    },
    {
      "feature": "Arm invalidation commands",
      "status": "SEMANTIC",
      "source": "Arm IHI 0070 H.a §§4.3–4.4",
      "module": "architecture/arm/model.mjs",
      "testFile": "tests/iommu-arm.test.mjs",
      "testId": "TLB invalidation scopes",
      "scope": "EL2 TLBIs and CMD_ATC_INV are consumed as not modelled; no EL2 regime or ATC"
    },
    {
      "feature": "Arm range invalidation",
      "status": "EXECUTABLE",
      "source": "Arm IHI 0070 H.a §4.4 / Linux __arm_smmu_tlb_inv_range",
      "module": "architecture/arm/records.mjs",
      "testFile": "tests/iommu-arm.test.mjs",
      "testId": "range invalidation follows __arm_smmu_tlb_inv_range",
      "scope": "TG/NUM/SCALE/TTL arithmetic as Linux issues it"
    },
    {
      "feature": "Arm shared-ASID TLB tagging",
      "status": "SEMANTIC",
      "source": "Arm IHI 0070 H.a §3.21",
      "module": "architecture/arm/model.mjs",
      "testFile": "tests/iommu-arm.test.mjs",
      "testId": "streams sharing an ASID and VMID share TLB entries",
      "scope": "TLB entries tagged by VMID and ASID, so streams that share them share entries"
    },
    {
      "feature": "Topology / Linux lifecycle",
      "status": "SEMANTIC",
      "source": "Lenovo LP1467 / Linux DMA API",
      "module": "architecture/shared/topology.mjs",
      "testFile": "tests/iommu-requests.test.mjs",
      "testId": "route evidence and scenario replay",
      "scope": "Synthetic routing; missing evidence remains inconclusive"
    },
    {
      "feature": "Silicon, PCIe fabric and firmware validation",
      "status": "HARDWARE_ONLY",
      "source": "AMD / Arm architecture",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "No physical hardware is exercised by browser tests"
    },
    {
      "feature": "52-bit addressing / PBHA / XNX",
      "status": "REFERENCE",
      "source": "Arm H.a §2.3",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.1; IDR5.VAX/OAS; IDR3.PBHA/XNX"
    },
    {
      "feature": "MPAM / S2FWB",
      "status": "REFERENCE",
      "source": "Arm H.a §2.4",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.2; IDR3.MPAM/FWB"
    },
    {
      "feature": "Enhanced CMDQ / ATS configuration events",
      "status": "REFERENCE",
      "source": "Arm H.a §2.5",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.3; IDR1.ECMDQ; IDR0.ATSRECERR"
    },
    {
      "feature": "Permission indirection / overlay / D128",
      "status": "REFERENCE",
      "source": "Arm H.a §2.8",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.4; Feature-specific IDR controls"
    },
    {
      "feature": "DCMDQ",
      "status": "REFERENCE",
      "source": "Arm H.a §2.9; §3.5.7",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.5; IDR6.DCMDQ (optional)"
    },
    {
      "feature": "Virtual → physical StreamID",
      "status": "REFERENCE",
      "source": "Arm H.a §2.9; §3.5.9",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.5; IDR6.VSID (optional)"
    },
    {
      "feature": "Memory-type transformation",
      "status": "REFERENCE",
      "source": "Arm H.a §2.9",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.5; IDR3.MTCOMB (mandatory v3.5)"
    },
    {
      "feature": "Dirty tracking / cleaning / VMALL",
      "status": "REFERENCE",
      "source": "Arm H.a §2.9; §§3.13.9–10",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.5; IDR3.HDBSS/HACDBS/TLBIW (optional)"
    },
    {
      "feature": "FNG interoperability",
      "status": "REFERENCE",
      "source": "Arm H.a §2.9",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.5; IDR3.FNG (mandatory v3.5)"
    },
    {
      "feature": "RME / GPT scaling / GDI",
      "status": "REFERENCE",
      "source": "Arm H.a §2.9; §3.25",
      "module": "",
      "testFile": "",
      "testId": "",
      "scope": "SMMUv3.5; ROOT_IDR0.APPSAA/NSO/GPTS/GDI (optional)"
    }
  ]
}