IOMMU / STATEFUL CACHE EXPERIMENTS
Which state did the request use?
Change a mapping, keep a cached copy, then follow the bytes or interrupt. A request can succeed and still reach the wrong destination.
Loading the experiment
What kind of claim is this?
OBSERVATION
No request yet
Try a different sequence
Manual actions pause the guided sequence. Reset to follow the lesson again. Draft edits need publication; maintenance needs consumption, application and observation.
“Local all” covers this fixture’s DTE and page caches. Endpoint ATC and interrupt entries have separate controls. Holding a dependency is a teaching schedule, not a command bit.
Inspect a moment
Viewing the live state.
1 · Request & result
2 · Backing & cache
Field values
3 · Maintenance
4 · Memory & route
5 · Logs & pending work
Log retirement, notification acknowledgement, repair and retry are separate actions.
Repair and comparison rules
To repair a reserved-bit fault, draft that bit as 0, publish it, submit the relevant DTE or page maintenance, consume, apply and observe completion, then send a new request. Clearing one bit preserves the other edits. Repair does not consume fault records or retry a terminated request.
A completed maintenance operation cannot evict newly filled state again. Submit a new operation for new work. Repeating an observation only inspects completion.
A cold comparison repeats the latest recorded eligible request in a separate branch against current published state. The branch identifies the source frame and intervening actions. Read/Write, identity, address, size and pattern stay attached to that request; local eviction is explicit.
The coherent comparison control explicitly reinitializes both payload views to 11 and returns ownership to the CPU. It preserves prior history and translation state. It is a teaching-fixture initialization, not a hardware coherency-mode switch; visibility still does not replace ordering.
Independent cold comparison
Expert evidence & export
Generation and sample IDs are simulator metadata. Raw records below are bounded semantic state, not hardware captures. History inspection does not reissue traffic.
The rules behind the experiments
Cold, stale and disabled mean different things. A cold entry is absent now. A stale entry differs from published backing. A resident entry might never be consulted if an earlier stage rejects the request. This simulator deliberately retains successful entries; hardware may evict or invalidate more broadly.
AMD guest permission promotion
With guest translation active, a cached guest permission denial requires a fresh guest-table walk. Granting guest Write permission can therefore work without a guest invalidation solely for that promotion. Revoking Write or removing a present page requires maintenance. Host and DTE restrictions remain effective, and an endpoint’s cached ATS translation has separate requirements. Hardware NpCache=0 does not mean failed lookups become persistent negative entries.
IRTE caching, live fields and Guest APIC
Setting supported IRTCacheDis does not flush previously cached entries. Once those entries are invalidated, new IRTEs are fetched without installing cache entries while the control stays set. In guest mode with GAEn=1, the vector and backing-page root may be retained while IsRun, Destination, GALogIntr, GAPPIDis and GATag (when present) are read live. IsRun and Destination are sampled together. The virtual IRR write, GA record and host notification are different effects; none proves that a CPU ran the handler.
Completion is a scoped guarantee
A consumed command is not necessarily completed work. A completed wait does not supply an omitted invalidation or correct the wrong target. A required endpoint response or matching in-flight dependency prevents completion here. Once the applicable protocol completes, the model cannot allow matching old work to escape as normal behaviour. There is no universal payload fence or safe page-reuse verdict.
Arm and payload coherency
Arm configuration invalidation (CFGI) and translation invalidation (TLBI) target different state. CMD_SYNC relates to applicable prior work on its queue; it does not establish endpoint visibility of CMD_PRI_RESP. The coherency lesson declares separate CPU/device views and ownership handoffs. Coherent memory still needs correct descriptor publication and ordering.
Scope: one retained entry per cache family, one selected requester and 4 KiB page pair; guest/host leaf snapshots are combined. No timing, general multi-entry replacement, arbitrary DomainID/range matching, real PCIe packets, GAPPI delivery, EOI or all optional Arm features. Wrong-target behaviour is a deliberately minimal teaching schedule. Use the Raw-records workbench for raw x2APIC formats, request patterns and additional buffer errors.
Sources: AMD 48882-PUB 3.11 §§2.2.5, 2.2.7.3, 2.4, 2.7; Control[59] and NpCache. Arm IHI 0070 H.a §§3.21, 4.3–4.5, 4.7.3. Linux DMA API HOWTO.